Chip gallery

Fully integrated class-D outphasing RF PA designed in ST 130nm CMOS:

5.5 V, +32.0 dBm, DE/PAE: 20.1/15.3 % at 1.85 GHz, 0.9 GHz 3 dB BW

Fully integrated class-D outphasing RF PA designed in ST 65nm CMOS:

5.5 V (6.0 V), +29.7 dBm (+30.5 dBm), DE/PAE: 30.2/26.6 % at 1.95 GHz, 1.6 GHz 3 dB BW

Class-D stage with harmonic suppression designed in ST 90nm CMOS:

1.2 V, +5.1 dBm, DE/PAE: 73/59 % at 0.9 GHz, 2.5 GHz 3 dB BW, >30 dB harmonic suppression

Class-D outphasing RF PA designed in ST 90nm CMOS:

1.3 V, +10.3 dBm, DE/PAE: 39/33 % at 0.9 GHz, 2.0 GHz 3 dB BW

Class-E RF PAs designed in Infineon 130nm CMOS:

1.5/1.0 V, +26.4/+22.7 dBm, PAE: 30/36 % at 1.85/2.45 GHz

Class-A RF PAs designed in Infineon 65nm CMOS:

3.3 V, +11.6/+9.4 dBm (average) at 2.4 GHz, 3.8 % EVM for 64-QAM